Synchronized charge pump-driven input buffer and method
US9973079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2014 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | May 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/496
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.