Method and apparatus for clock frequency multiplier
US9973178B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a clock frequency doubler, an input clock feeds into a digital programmable delay circuit, and an inverted input clock feeds into another digital programmable delay. The outputs of these digital programmable delay circuits are combined with the input clock and inverse clock through AND gates in order to generate clock pulses at both the rising and falling edge of the clock. These signals are combined using an OR gate to provide an output clock signal with a frequency that is double the frequency of the input clock signal. The values of the control bits for the digital programmable delay circuit are determined in a time-to-digital conversion (TDC) circuit that includes a Successive Approximation Register (SAR). For every cycle of the clock, the SAR circuit successively sets the programmable delay control bits and compares the delay circuit output with the input clock to determine the value of the control bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.