Patent · US Active

Clock synchronizer

US9973196B2 · kind B2 · utility

0Cited by

7References

10Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Jos Verlinden · Wachtendonk, DE
Remco Cornelis Herman van de Beek · Eindhoven, NL
Stefan Mendel · Graz, AT

Key dates

Filing date	Mar 30, 2016
Grant date	May 15, 2018
Priority date	—
Expiry date	Mar 30, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH04W4/80
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.