Partial zero forcing equalization
US9973354B1 · kind B1 · utility
1Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jun 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03624
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In certain embodiments, an apparatus may comprise a circuit configured to receive a plurality of samples of an input signal. The circuit may update one or more equalizer parameters using partial zero forcing equalization. Further, the circuit may generate an equalized signal based on the plurality of samples of the input signal and the one or more equalizer parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.