Slicer and decision feedback equalization circuitry
US9973356B1 · kind B1 · utility
9Cited by
0References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.