Method and an apparatus for memory address allignment
US9977737B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Dec 25, 2013 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Jan 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked address pointer determined in accordance with the applied modulo arithmetic, is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.