Patent · US Active

Transistors having offset contacts for reduced off capacitance

US9978747B2 · kind B2 · utility

0Cited by
1References
11Claims
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Assignee

Inventor

Key dates

Filing dateSep 30, 2016
Grant dateMay 22, 2018
Priority date—
Expiry dateSep 30, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A transistor stack includes first and second doped regions serving as a source and drain, respectively of a transistor, an elongated gate structure including a first gate structure disposed between the first and second regions and serving as a gate of the transistor, a first set of electrical contact pads disposed on the first region, and a second set of electrical contact pads disposed on the second region, the second set of contact pads having an offset position with respect to the first set of contact pads in a longitudinal direction of the first and second regions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.