Method to improve device performance for FinFET
US9978749B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor structure comprising multiple fins and a gate structure on the fins. The method also includes removing a portion of the fins not covered by the gate structure to form a remaining portion of the fins, performing a first epitaxially growth process to form first epitaxially grown regions on the remaining portion of the fins, performing a first annealing process so that an upper portion of the first epitaxially grown regions is greater than a lower portion, performing a second epitaxially growth process on the annealed first epitaxially grown regions to form second epitaxially grown regions, and performing a second annealing process on the second epitaxially grown regions, so that an upper portion of the second epitaxially grown regions is greater than a lower portion. The second epitaxially grown regions are separated from each other before and after the second annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.