Buffer circuit and electronic device using same
US9979398B2 · kind B2 · utility
0Cited by
18References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 2015 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | May 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017509
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.