Adaptively reconfigurable time-to-digital converter for digital phase-locked loops
US9979405B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.