Logical L3 processing for L2 hardware switches
US9979593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2015 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Apr 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/72
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for learning a MAC address of an end machine that is logically connected to a logical network is described. The method receives configuration data for implementing a distributed logical router having different logical ports each of which is associated with a logical port of a logical switch. The method receives a packet through a first logical port of the logical router that has a destination IP address associated with a particular logical switch that is associated with a second logical port of the logical router. In order to learn the MAC address of the end machine, the method sends a first broadcast packet with a first source MAC address to a first set of forwarding elements that implements the particular logical switch, and sends a second broadcast packet with a second source MAC address to a second set of forwarding elements that also implements the particular logical switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.