Pipeline processor and an equal model compensator method and apparatus to store the processing result
US9983932B2 · kind B2 · utility
0Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Dec 30, 2010 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jul 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.