Detecting degraded core performance in multicore processors
US9983966B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2015 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Feb 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.