Arithmetic processing device and method for controlling arithmetic processing device
US9983994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.