Mapping processing method for a cache address in a processor to provide a color bit in a huge page technology
US9984003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.