Technique for compact and accurate encoding trim geometry for application in a graphical processing unit
US9984496B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Sep 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2219/2021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an example embodiment, a technique is provided for encoding trim geometry for application in a GPU. For a UV trim polygon associated with a surface, the UV trim polygon is recursive subdivided into a predetermined number of tiles to produce a set of tiles. Each tile of set of tiles is represented by a value in an array, where the value indicates whether the area of the UV trim polygon corresponding to the tile is entirely solid, is entirely void, or for a case where the tile includes both a solid portion and a void portion, provides an index into an associated linear trim array that stores a trim expression. The set of tiles, and the portions of the linear trim array pointed therefrom, are applied in the GPU to render a trimmed representation of the surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.