Design-aware pattern density control in directed self-assembly graphoepitaxy process
US9984920B2 · kind B2 · utility
1Cited by
48References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jul 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.