Array substrate
US9985053B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display apparatus including the array substrate. The array substrate includes: a plurality of signal lines aligned in a display area of the array substrate; a plurality of signal pads aligned in a non-display area of the array substrate; a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads; a plurality of auxiliary lines respectively overlapping and insulated from the fan-out lines; and a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.