Array substrate and display device
US9985054B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jan 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an array substrate and a display device that can suppress the adverse effects in display due to difference in gray-scale luminance of adjacent two rows caused by variation in capacitance of adjacent two rows of TFTs as the result of displacement of the data lines. Scan lines and data lines crossing each other are arranged on the array substrate. Each row of the scan lines is provided with a gate driver circuit, wherein each row of the scan lines is further provided with a compensation capacitor connected to the gate driver circuit, the compensation capacitor including a first metal layer and a second metal layer that are overlapped with each other to form an overlap region at which the first metal layer is isolated from the second metal layer by an insulation layer, wherein the compensation capacitor in an Nth row has a capacitance that changes in a direction opposite to the direction in which the capacitance of the compensation capacitor in an N+1th row changes, and the compensation capacitor in the Nth row has a capacitance that changes in the same direction as the direction in which the capacitance of a thin film transistor capacitor in the N+1th …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.