Sampling implementation method and device based on conventional sampling goose trip mode
US9985428B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H7/261
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Sampling implementation method and device based on conventional sampling GOOSE trip mode. CPU of master NPI plug-in, after receiving a second pulse, transmits sampling pulse generation time and a transmission enable bit to FPGA of the master NPI plug-in at a fixed interval; after detecting the transmission enable bit, the FPGA of the master NPI plug-in judges whether time of its internal timer is greater than/equal to the sampling pulse generation time, if yes, generates a sampling pulse to FPGA of collection plug-in; after receiving sampling pulse, the collection plug-in carries out A/D sampling, and transmits sampled data to the master NPI plug-in; when detecting that all A/D samplings are completed, the master NPI plug-in transmits data packets to protection CPU plug-in. The device includes an MMI plug-in, a protection CPU plug-in, a master NPI plug-in and a collection plug-in. Protection maloperation is thereby reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.