Patent · US Active

Programmable sequence controller for successive approximation register analog to digital converter

US9985640B1 · kind B1 · utility

9Cited by
8References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 25, 2017
Grant dateMay 29, 2018
Priority date
Expiry dateOct 25, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M1/466
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.