Systems and methods for evaluating errors and impairments in a digital-to-analog converter
US9985641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | May 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments of the present invention pertain to circuitry provided in a digital-to-analog converter (DAC) for carrying out measurements indicative of various performance characteristics of the DAC. In one exemplary implementation, a control circuit containing one or more switches is used to controllably route into a measurement system, a portion of a signal that straddles a boundary between a first digital data bit and a second digital data bit in a sequence of digital data bits that are received in a DAC cell of the DAC. The control circuit, which can be included in one or more DAC cells of the DAC, is connected to a branch of a differential circuit that is provided in each of the DAC cells of the DAC, in a manner that does not affect digital-to-analog conversion in the DAC cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.