System on chip and verification method thereof
US9990205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.