Multi-level memory mapping

US9990281B1 · kind B1 · utility

Assignee

• SAP SE · DE

Inventors

• Daniel Booss · Angelbachtal, DE
• Ivan Schreter · Malsch, DE
• Robert Kettler · Heidelberg, DE

Key dates

• Filing date: Nov 29, 2016
• Grant date: Jun 5, 2018
• Expiry date: Dec 9, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1016
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system for memory allocation and deallocation with a multi-level memory map is provided. In some implementations, the system performs operations comprising allocating a memory map for addressing a plurality of memory locations in a heap, the memory map comprising a root node, one or more second-level nodes, and a plurality of third-level nodes. The plurality of third-level nodes can comprise third entries for pointing to the memory locations and/or the one or more second-level nodes can comprise a plurality of second entries corresponding to the plurality of third-level nodes. The operations can further include determining a location to store data within the heap and/or tracking the location by placing a pointer within a third-level node of the plurality of third-level nodes and incrementing a counter corresponding to the third-level node. Related systems, methods, and articles of manufacture are also described.