Low power corruption of memory in emulation
US9990452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.