Pulse-stretcher clock generator circuit for high speed memory subsystems
US9990984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Dec 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.