Bonding pad arrangement design for multi-die semiconductor package structure
US9991227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Dec 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.