Patent · US Active

Dynamic current limit circuit

US9991784B2 · kind B2 · utility

0Cited by

5References

23Claims

0Family size

Assignee

Dialog Semiconductor (UK) Limited · GB

Inventors

Mark Childs · Swindon, GB
Martin Faerber · Munich, DE
Jens Masuch · Munich, DE
Giulio de Vita · Munich, DE

Key dates

Filing date	Sep 2, 2016
Grant date	Jun 5, 2018
Priority date	—
Expiry date	Sep 2, 2036

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02B70/10
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.