Master-slave flip-flop
US9991876B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.