Patent · US Active

Sampling phase-locked loop (PLL)

US9991897B1 · kind B1 · utility

5Cited by

15References

23Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Dongmin Park · San Diego, US
Jong Min Park · Sterling Heights, US
Yiwu Tang · San Diego, US

Key dates

Filing date	Jan 25, 2017
Grant date	Jun 5, 2018
Priority date	—
Expiry date	Jan 25, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0331
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.