Inter-layer reference picture restriction for high level syntax-only scalable video coding
US9992493B2 · kind B2 · utility
20Cited by
10References
36Claims
0Family size
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Key dates
| Filing date | Mar 27, 2014 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In one implementation, an apparatus is provided for encoding or decoding video information. The apparatus comprises a memory unit configured to store reference layer pictures associated with a reference layer, an enhancement layer, or both. The apparatus further comprises a processor operationally coupled to the memory unit. In one embodiment, the processor is configured to restrict usage of at most one reference layer pictures that has been resampled as an inter-layer reference picture, and predict a current picture using inter-layer prediction and the inter-layer reference picture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.