Time division duplex (TDD) subframe structure supporting single and multiple interlace modes
US9992790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Jun 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure provide a time division duplex (TDD) subframe structure that supports both single and multiple interlace modes of operation. In a single interlace mode, control information, data information corresponding to the control information and acknowledgement information corresponding to the data information are included in a single subframe. In a multiple interlace mode, at least one of the control information, the data information corresponding to the control information or the acknowledgement information corresponding to the data information is included in a different subframe. Both single and multiple interlace modes can be multiplexed together within the TDD subframe structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.