Patent · US Active

System and method of implementing finite difference time domain models with multiple accelerated processing components (APCS)

US9995835B2 · kind B2 · utility

1Cited by
17References
25Claims
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Key dates

Filing dateJul 17, 2013
Grant dateJun 12, 2018
Priority date—
Expiry dateMay 1, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01V2210/673
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Embodiments of a method for implementing a finite difference time domain modeling with multiple APCs are disclosed herein. The disclosed methods and systems overcome the memory capacity limitation of APCs by having each APC perform multiple timesteps on a small piece of the computational domain or data volume in a APC queued manner. The cost of transferring data between host and compute accelerator can then be amortized over multiple timesteps, greatly reducing the amount of PCI bandwidth required to sustain high propagation speeds. The APC queued nature of the algorithm achieves linear scaling of PCI throughput with increasing number of APCs, allowing the algorithm to scale up to many dozens of APCs in some embodiments.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.