Data recovery in memory having multiple failure modes
US9996417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.