Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect
US9996490B2 · kind B2 · utility
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9References
22Claims
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Key dates
| Filing date | Sep 19, 2013 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.