Scalable and programmable processor comprising multiple cooperating processor units
US9996499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2011 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.