Secure computer architecture
US9996709B2 · kind B2 · utility
0Cited by
30References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A secure computer architecture is provided. With this architecture, data is received, in a component of an integrated circuit chip implementing the secure computer architecture, for transmission across a data communication link. The data is converted, by the component, to one or more first fixed length frames. The one or more first fixed length frames are then transmitted, by the component, on the data communication link in a continuous stream of frames. The continuous stream of frames includes one or more second fixed length frames generated when no data is available for inclusion in the frames of the continuous stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.