Common circuit for GOA test and eliminating power-off residual images
US9997117B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Feb 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0408
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention discloses a common circuit for GOA test and eliminating power-off residual images, including a first test end (3), a test signal line (AT1) connected to the first test end (3), a second test end (5), a feedback signal line (AT2) connected to the second test end (5), and the same number of test TFTs (T0) as cascade GOA unit circuits. By connecting the gate of each test TFT (T0) to test signal line (AT1), the source to feedback signal line (AT2) and the drain to the output end of corresponding GOA unit circuit and gate scan line, the invention can test the output signal of any stage GOA unit circuit to determine the location of a malfunctioning GOA unit circuit, and releasing the residual charges of the liquid crystal capacitor and storage capacitor at the display area of LCD panel when powering off to eliminate residual images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.