Read assist circuit with process, voltage and temperature tracking for a static random access memory (SRAM)
US9997236B1 · kind B1 · utility
18Cited by
1References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.