Semiconductor memory devices
US9997462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Apr 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.