Semiconductor device layout structure

US9997510B2 · kind B2 · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventors

• Chi-Li Tu · Hengshan, TW
• Ching-Wen Wang · Taipei, TW
• Karuna Nidhi · Patna, IN

Key dates

• Filing date: Sep 9, 2015
• Grant date: Jun 12, 2018
• Expiry date: Sep 26, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.