Semiconductor memory device and manufacturing method thereof
US9997524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.