Three-dimensional semiconductor memory device and method of fabricating the same
US9997530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2015 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.