Mram memory device and manufacturing method thereof
US9997562B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Mar 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.