MOS-based power semiconductor device having increased current carrying area and method of fabricating same
US9997599B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2014 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/154
Abstract
A semiconductor device includes a substrate, a drift region, a source region, a gate region, a drain contact and a base region. The substrate is doped with a first dopant type. The drift region is disposed above the substrate, and is doped with the first dopant type. The source region, doped with the first dopant type. The gate region is disposed above the drift region and above the source region. The base region is disposed between the source region and the drift region. At least a portion of the base region includes at least one trench having a vertical wall and a horizontal wall. The base region is further configured to conduct current in a horizontal direction on the vertical wall and in a horizontal direction the horizontal wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.