Porous SiOx materials for improvement in SiOx switching device performances
US9997705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2014 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Nov 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.