Clock calibration using asynchronous digital sampling
US9998125B2 · kind B2 · utility
12Cited by
8References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.