PLL post divider phase continuity
US9998129B1 · kind B1 · utility
6Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.