Cooling system and circuit layout with multiple nodes
US9999162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/20172
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit layout includes two or more high performance processing nodes that are cooled by a cooling fan. The cooling fan resides in a cooling fan assembly that relies on principles of aerodynamics to maximize airflow. The cooling fan assembly is coupled to the opposite side of a backplane to which the circuit layout is mounted. The backplane includes large ventilation holes to permit the cooling fan to induce significantly more airflow across the circuit layout than possible with conventional designs. At least one advantage of the approaches discussed herein is circuit layouts can be constructed to meet the competing objectives of high node performance and high node density. Accordingly, data centers can be built that offer high performance computing without requiring a significant increase in physical real estate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.