Triple-slope analog-to-digital converters
USRE28706E · kind E · reissue
Assignee
Inventor
Key dates
| Filing date | May 23, 1975 |
| Grant date | Feb 3, 1976 |
| Priority date | — |
| Expiry date | May 23, 1995 |
Classification
- Technology area (CPC —)General
Abstract
A ramp type analogue to digital converter including an integrating circuit the output of which is first set to a level dependent upon the magnitude of an analogue input voltage to be converted. A reference signal is then applied to ramp down the integrator output level to a datum level and the conversion is effected by counting clock pulses while the integrator output is ramping down to datum level. The magnitude of the reference signal and the numerical weighting of the clock pulses being counted are scaled down by a common factor when the ramp reaches a value close to the datum level so that the slope of the ram is reduced and the resolution of conversion is increased as it approaches datum. Thus, compared with a ramp type digital voltmeter having a constant slope discharge ramp and a given resolution, the discharge time is reduced for the same resolution of conversions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.